The present invention relates to a method of fabricating a semiconductor device having, as components, a polysilicon film implanted with an n-type impurity and a polysilicon film implanted with a p-type impurity, each of the polysilicon films being formed on a single semiconductor substrate.
In recent years, MOS-type integrated circuits have been used in a growing number of digital circuits. Among the MOS-type integrated circuits, a CMOS device in which a pMOS transistor and an nMOS transistor are integrated has been used frequently because of its extremely low power consumption. The CMOS device or the like has a structure in which a polysilicon film implanted with an n-type impurity and a polysilicon film implanted with a p-type impurity are provided as components on a single semiconductor substrate. For example, there has been known a dual-gate CMOS device in which the gate electrode of an n-channel MOS transistor is doped with an n-type impurity and the gate electrode of a p-channel MOS transistor is doped with a p-type impurity.
FIGS. 6(a) to (d) are cross-sectional views illustrating the process of fabricating a conventional dual-gate CMOS device.
In the step shown in FIG. 6(a), a gate oxide film 102 is formed by thermal oxidation on a semiconductor substrate 102 to extend over a pMOSFET region Rp and an nMOSFET region Rn.
Next, in the step shown in FIG. 6(b), a polysilicon film 103 is deposited by CVD on the gate oxide film 102.
Next, in the step shown in FIG. 6(c), phosphorous ions (P+) are implanted into a portion of the polysilicon film 103 included in the nMOSFET region Rn by using a resist film, whereby an n-type implanted region 104a is formed in a near-surface region of the polysilicon film 103. Subsequently, boron ions (B+) are implanted into a portion of the polysilicon film 103 included in the pMOSFET region Rp by using a resist film, whereby a p-type implanted region 104b is formed in a near-surface region of the polysilicon film 103.
Next, in the step shown in FIG. 6(d), the polysilicon film 103 and the gate oxide film 102 are patterned by etching to form an n-type gate electrode 105 of an n-channel MOS transistor and a p-type gate electrode 106 of a p-channel MOS transistor.
In the process of fabricating the conventional dual-gate CMOS device, however, the phenomenon was observed in the step shown in FIG. 6(d) in which side etching occurred at both ends of the n-type implanted region 104a overlying the n-type gate electrode 105. The following is the result of assuming the cause of such a phenomenon.
After the process of ion implantation in the step (c), annealing is not normally performed prior to the subsequent step (d). This is for preventing boron penetration into the substrate as a result of diffusion. As a consequence, phosphorus and boron are present at high concentrations in the n-type implanted region 104a and in the p-type implanted region 104b. If etching is performed under such conditions, it may be considered that the amount of etching in the n-type implanted region 104a (upper part) containing phosphorus at a high concentration becomes larger than the amount of etching in the other portion (lower part) of the n-type gate electrode 105. If the size of the lower part of the n-type gate electrode 105 along the gate length is adjusted to 100 nm to 150 nm, the size of the upper part of the n-type gate electrode 105 (n-type implanted region 104a) along the gate length becomes 70 nm to 130 nm. Since side etching is observed in the upper part of the n-type gate electrode 105, if the gate electrode 105 is covered with nitride sidewalls or the like thereafter, voids may be formed in the side surfaces of the gate electrode. In the case of adopting a polycide structure in which a silicide film is provided on the polysilicon film to compose the gate electrode, side etching observed in the upper part of the n-type gate electrode 105 may degrade the adhesion between the polysilicon film and the silicide film. In the case of adopting a polymetal structure in which a metal film is provided on the polysilicon film to compose the gate electrode, side etching observed in the upper part of the n-type gate electrode 105 may degrade the adhesion between the polysilicon film and the metal film.
It is to be noted that side etching was not observed in the upper part of the p-type gate electrode 106. This may be because the manner in which silicon and boron are bonded is considered to be different from the manner in which silicon and phosphorus are bonded.
Such a phenomenon is not limited to the gate electrode and may also occur with a capacitor having an interconnect composed of a polysilicon film and an electrode composed of a polysilicon film.
It is therefore an object of the present invention to suppress, in a method of fabricating a semiconductor device having members composed of polysilicon films containing n-type and p-type impurities, such as a gate electrode and an interconnect, the occurrence of side etching in patterning the member composed of the polysilicon film containing an n-type impurity, while preventing a problem caused by boron diffusion.
The method of fabricating a semiconductor device comprises the steps of: (a) forming a polysilicon film on a semiconductor substrate; (b) implanting an n-type impurity into a portion of the polysilicon film; (c) performing a heat treatment for diffusing the n-type impurity with respect to the polysilicon film; (d) after the step (c), implanting a p-type impurity into another portion of the polysilicon film; and (e) after the step (d), patterning the polysilicon film by etching.
In accordance with the method, the n-type impurity has been diffused satisfactorily when the polysilicon film doped with the n-type impurity is patterned, so that the upper end portion of the polysilicon film is inhibited from being etched greatly in the lateral direction by the patterning. Consequently, the patterning of the polysilicon film does not cause side etching in the upper end portion of the formed member. This prevents an increase in the resistance of the member formed by patterning the polysilicon film. Since a heat treatment for simultaneously diffusing the n-type impurity and the p-type impurity has not been performed, the entrance of the p-type impurity from the polysilicon film into the semiconductor substrate that might be caused by the heat treatment is inhibited. In the case of using a MOS transistor, therefore, a semiconductor device with stable properties including threshold value can be fabricated.
The method further comprises the step of: prior to the step (a), forming a gate insulating film on the semiconductor substrate, wherein an n-type gate electrode and a p-type gate electrode are formed by the patterning in the step (e) such that the semiconductor device functioning as a dual gate transistor is formed. As a result, the upper and lower parts of the gate electrode are etched uniformly so that voids are not formed around the gate electrode even when nitride sidewalls, a cobalt silicide film, or the like is provided around the gate electrode. Since a heat treatment for simultaneously diffusing the n-type impurity and the p-type impurity has not been performed, the entrance of the p-type impurity from the gate electrode into the semiconductor substrate that might be caused by the heat treatment is inhibited. As a result, a transistor with stable properties including threshold value can be fabricated.
Preferably, a temperature range for the heat treatment in the step (c) is 750 to 850xc2x0 C.
If the method further comprises the step of: forming a silicide film or a metal film on the polysilicon film, excellent adhesion can be maintained between the polysilicon film and silicide or between the polysilicon film and the metal film.